(1) Field of the Invention
This invention relates to semiconductor structures and circuits, and in particular to a decoupling circuit for a charge-coupled line-addressable random-access memory.
(2) Prior Art
The development of charge-coupled devices (referred to hereinafter as CCD's) has been described in numerous articles and technical publications. See, for example, the article by Gilbert F. Amelio entitled "Charge-Coupled Devices," published in the February 1974 Scientific American, Vol. 230, No. 2; and Charge Transfer Devices, by Sequin and Tompsett, published by the Academic Press in 1975. It is possible in the CCD art to fabricate long shift registers having stages consisting of individual charge-storage elements. Such shift registers may be used in area image sensors, analog delay lines or line scan arrays. When strings of charge-storage elements are organized in a parallel format and additional circuitry is provided for addressing, writing, or reading out information, such arrangements of CCD elements may be utilized as essentially random-access memories.
The organization of line-addressable random-access memory (hereinafter LARAM) is like that of a random-access memory except that lines of charge-coupled elements are accessible rather than individual bits of information. Although for this reason a LARAM does not allow true random-access to every bit in every shift register, the circulation of bits within a given shift register may be conducted at such high frequencies, for example five to ten megaHertz, that actual access time to any one element within a shift register can be on the order of microseconds. The exact access time depends on the length of the shift register and the particular clock frequency with which the elements are transferred. A more detailed explanation of a line-addressable random-access memory may be found in U.S. Pat. No. 4,024,512, issued to Gilbert F. Amelio and assigned to Fairchild Camera and Instrument Corporation, the assignee of this invention.
One of the difficulties of prior-art LARAM's has been the decoupling of the shared output diode with its large capacitance loading from the sense node of a comparator circuit used to interpret the output signals as either logical zeros or ones. A prior-art comparator circuit is shown in FIG. 6 of the U.S. Pat. No. 4,024,512, mentioned above.
Two prior-art approaches to sensing the CCD output charge are direct coupling and coupling through an MOS transmission device, as shown in FIGS. 3A and 3B, respectively. In FIG. 3A, an example of direct coupling between the output diode and the sense node, the charge from the CCD storage elements is transferred by shift registers (not shown) connected to output lines 30a, 30b, . . . 30n to a source, or output diode, of transistor 31. The signal then appears as a voltage shift at terminal L. The change in voltage due to the presence of a signal on one of the CCD output lines will be given by: EQU .DELTA.V = Q.sub. signal /C.sub.L
where Q.sub.signal is the signal charge and C.sub.L is the capacitance at terminal L. Because C.sub.L typically is large (on the order of several hundred femtofarads), the change in voltage .DELTA.V caused by a signal on one of the CCD lines will be small. A small .DELTA.V is undesirable as it necessitates a sensitive, more complex, and hence, by virtue of yield, expensive, comparator circuit to obtain reliable performance in the decoding of CCD signals.
FIG. 3B shows the second prior-art technique for decoupling the sense node from the output diode, which is to connect the source and drain of an MOS transistor 33 between the shared output diode (source of transistor 32) and the sense node SN of the comparator circuit. The gate of transistor 33 is connected to a constant voltage source to place transistor 33 at turnoff when no signal is present. The appearance of signal charge at point L will turn on transistor 33 allowing Q.sub.signal to transfer to SN. In the ideal case, the change in voltage resulting from the presence of a CCD signal can be represented by: EQU .DELTA.V = Q.sub.signal /C.sub.SN
where C.sub.SN is the capacitance at terminal SN and C.sub.SN &lt;&lt;C.sub.L. Unfortunately, such circuits, although providing a significantly larger change in voltage at the sense node of the comparator circuit as a result of the presence of a signal from the CCD device, are slow in operation. The slowness is caused by the necessity of operating MOS transistor 33 very near its turnoff point where its transconductance is very low.